(a) Field of the Invention
The present invention relates to a method for testing a nonvolatile semiconductor memory device and, more particularly, to a method for testing a nonvolatile semiconductor memory device, such as a flash memory, which has an array of memory cell transistors each capable of accumulating charge therein for programming.
(b) Description of the Related Art
A nonvolatile semiconductor memory device, such as a flash memory, capable of erasing whole programmed data at a time includes a plurality of memory cells, each composed of a MOS FET having a polycrystalline silicon double-layer gate structure. The double-layer gate structure is composed of a tunnel oxide film, a floating gate made of polycrystalline silicon, an inter-gate insulating film, and a control gate made of polycrystalline silicon. These are formed on a p-type silicon substrate, by using a silicon thermal oxidation technique, a thin film forming technique such as CVD, photolithography, a thin film dry etching technique, and the like. The source and drain diffusion regions of the MOS FET are formed by an ion implantation technique using phosphorous or arsenic dopant.
To program a memory cell, the source electrode (hereinafter, simply referred to as "source", the same simplification will be applied to other electrodes) of the memory cell is grounded, and the drain and control gate of the memory cell are supplied with high voltages, for example, 6 V and 12 V, respectively, so as to inject channel hot electrons, which are generated at the drain-side end of the channel of the memory cell, into the floating gate, thereby increasing the threshold voltage of the memory cell as viewed from the control gate. To erase a memory cell, a negative high voltage of about -20 V is applied to the control gate, or a positive high voltage of about 7 V is applied to the source so as to discharge electrons accumulated on the floating gate by utilizing the Fowler-Nordheim tunnel effect, thereby decreasing the threshold voltage of the memory cell as viewed from the control gate.
In a nonvolatile semiconductor memory device having a memory array in which memory cells each having the structure as described above are disposed in a matrix, namely, in the row and column directions, more specifically, in a flash memory, a plurality of memory cells can be erased together at a time. In this case, however, the threshold voltages of the memory cells after the erasure vary depending on a variation in the erasing characteristics of the memory cells. If the variation is too large, some of the memory cells will have a threshold voltage lower than 0 V after the erasing operation, which state is generally called over-erasure. If an over-erased memory cell exists in a memory cell array due to an overall erasure operation, it will be impossible to read out data from the remaining memory cells which are connected to the same bit line to which the over-erased memory cell is connected.
To overcome the problem as described above, it is necessary prior to a commercial production to measure the erasing characteristics of many memory cells each having a similar size, cheek the variation in the thresholds of the memory cells after an overall erasure operation, and analyze the cause of the variation. However, when a large scale test pattern is prepared including a memory block of an actual memory cell array and a control circuit for controlling the memory cell array, time period required for manufacture of the test pattern will be large, which greatly decreases the efficiency of the analysis of the nonvolatile memory device. Accordingly, a test pattern and a program for test procedure thereof have been desired which can efficiently evaluate the variation in the erasing characteristics of the nonvolatile semiconductor memory device.
FIGS. 1A and 1B are circuit diagrams of a memory cell block or row in a nonvolatile semiconductor memory device to be tested. These figures show the block at the steps in a test method called CAST (cell array stress test) in which memory cells in each block are connected in parallel (refer to P. Cappelletti et al., "CAST: an electrical stress test to monitor single bit failures in flash-EEPROM structures", The 13th Annual IEEE Nonvolatile Semiconductor Memory Workshop, 1994).
In the test method for a nonvolatile semiconductor memory device as mentioned above, a test block or test row R1 is formed including a plurality of memory cells MC arrayed in a row and each having a control gate CG connected together, as shown in FIG. 1A. The sources S of the memory cells MC in the test row R1 are connected together to form a common source line 12 connected to the ground GND, while the drains of the memory cells MC in the test row R1 are connected together to form a common drain line 13. After initializing the memory cells MC in the test row R1 into programmed states, a gate voltage VG of about -20 V is applied to the word line 14 while maintaining the common drain line 13 in an open state or floating state (OP), to thereby erase the memory cells MC of the test row R1.
Subsequently, as shown In FIG. 1B, a programming supply voltage (V.sub.D) of about 1 V is applied to the common drain line 13, following which the voltage (VG) applied to the word line 14 is gradually raised while measuring current ID flowing through the common drain line 13, which current is the sum of the drain current of all the memory cells MC in the test row R1. The current will be referred to as total drain current, hereinafter.
FIG. 2 is presented for explaining expected curves of the measured total drain current ID as a function of the gate voltage VG1 in the test as described above, in which curve I including a solid line section Ia and a broken line section Ib represents a transfer characteristic of an over-erased memory cell, curve II including a solid line section IIa and a broken line section IIb represents the total drain current after erasure of the test row including no over-erased memory cell, and curve III represents the total drain current before an overall erasure or after overall programming. As is understood from FIG. 2, an over-erased memory cell exhibits a negative threshold characteristic in which it provides drain current at a negative gate voltage to show the defect therein.
If an over-erased memory cell 11 exists in the test row R1 having a negative threshold voltage, which is sometimes caused by the prior overall erasing operation, the total drain current ID varies along the solid line section Ia of curve I and then along the solid line section IIa of curve II as the ate voltage VG1 increases. On the other hand, if there is no over-erased memory cell, the total drain current ID varies along broken line section IIb and then solid line section IIa of curve II. Based on the difference between these characteristic curves, it can be judged whether or not an over-erased cell exists in the test row R1.
The conventional test method as described above is used because the structure of a test block and the procedures of the test is simple. Namely, it is unnecessary to prepare a large scaled test pattern so that the processing time required for the trial manufacture can be small and the evaluation and analysis of the test block can be performed efficiently.
In the conventional method as described above, only the total drain current of the test block is measured after the erasing operation. That is, it is impossible to separately measure the characteristics of the over-erased memory cell 11 and the characteristics of other normally erased memory cells although it is possible to judge whether or not an over-erased memory cell exists. It is, however, desired to measure the tunnel current characteristic of the tunnel oxide film of the over-erased memory cell for a further analysis on the erasing characteristic of the over-erased memory cell to thereby manufacture a nonvolatile memory cell device having stable programming and erasing characteristics.
If the analysis of tunnel current characteristic of the tunnel oxide film is desired for the over-erased cell by using the conventional method, a large scale pattern must be prepared, and the erasing characteristics of all the memory cells must be measured one by one in the test row. In this case, after localizing an over-erased cell based on the results of the measurement, a further measurement must be performed on the tunnel characteristic of the tunnel oxide film of the localized memory cell. Due to these complex steps, the efficiency of the analysis greatly decreases.